
ICS8430S07AKI REVISION A SEPTEMBER 3, 2009
13
2009 Integrated Device Technology, Inc.
ICS8430S07I Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform ance,
power supply isolation is required. The ICS8430S07I provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. VDD, VDDA and VDDO_X should be
individually connected to the power supply plane through vias, and
0.01F bypass capacitors should be used for each pin. Figure 2
illustrates this for a generic VDD pin and also shows that VDDA
requires that an additional 10
resistor along with a 10F bypass
capacitor be connected to the VDDA pin.
Figure 2. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k
resistor can be tied from CLK to ground.
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k
resistor can be tied from
XTAL_IN to ground.
LVCMOS Control Pins
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1k
resistor
can be used.
Outputs:
LVPECL Outputs
The unused LVPECL output can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
LVCMOS Outputs
All unused LVCMOS output can be left floating. There should be no
trace attached.
VDD
VDDA
3.3V
10
10F
.01F